Various Embodiments of the present disclosure generally relate to semiconductor memory devices and methods of testing open failures thereof.
Semiconductor integrated circuit devices may be fabricated using a plurality of unit processes and may be classified into good chips or failed chips through a function test. The function test may be performed to evaluate functions of peripheral circuits and memory cells constituting the semiconductor integrated circuit devices. Most of the semiconductor integrated circuit devices may tend to exhibit single bit fails more than dual bit fails. Accordingly, as the semiconductor integrated circuit devices increases a density of integration, test time of the highly integrated semiconductor integrated circuit devices have been more increased. Hence, a parallel test has been proposed to reduce the test time. The parallel test may be performed by simultaneously writing the same data into a plurality of memory cells of the semiconductor memory device and by simultaneously reading out the data stored in the plurality of memory cells. Thus, the parallel test may reduce the test time.
In general, test input/output (I/O) lines in addition to global I/O lines may be required to perform the parallel test. That is, when a read operation is executed in the parallel test mode, the data stored in the memory cells may be loaded on a plurality of test I/O lines and the data levels on the plurality of test I/O lines may be detected or sensed to discriminate whether at least one of the memory cells normally operate or not. That is, when the parallel test is performed, the data stored in the memory cells may be outputted through the test I/O lines instead of the global I/O lines through which the data stored in the memory cells are outputted in a normal read mode.